1. Technical Field
Embodiments of the inventive subject matter generally relate to the design of an integrated circuit (IC) chip, and more specifically, to optimizing connection constraints in an integrated circuit design.
2. Description of the Related Art
Typically, large scale integrated circuits contain millions of logic gates. FIG. 1 shows the spatial structure of an existing IC chip, the bottom of the chip is a base layer consisting of transistors and the upper layer is a metal layer consisting of metal connections.
In the design process of an integrated circuit, the first step is register transfer level (RTL) coding. The RTL coding is then encoded into a gate-level netlist containing devices and connections of chips by an IC design tool, such as a Synopsys® Design Compiler® tool. The process of encoding the RTL coding into a gate-level netlist may be referred to as synthesizing. Finally, operations for placement of chip devices and connecting the chip devices (also referred to as routing, wiring or lining) are performed.
Based on the connection, the IC design tool will provide connection constraints before connecting, where the connection constraints include the length of the connection, the number of the metal layer at which the connection is located, and the width of the connection. In this manner, the IC design tool can automatically perform connections for the whole design in accordance with the requisite connection constraints. If the connection resource provided by a metal layer in a certain region of a chip (e.g., the amount of metal area required to create the requisite connections), is less than the requisite connection resource, the region of the chip is deemed to suffer from “congestion” or is deemed to be “congested.” Generally, a congestion matrix, a list of congestion values associated with different regions on the chip, or a congestion map can be used to describe the severity of the congestion and the position/location of the congestion on the chip.
Back-end design of a general-purpose integrated circuit chip typically comprises two processes—timing closure and physical closure. Timing closure can refer to the process for ensuring that all the logical units in a circuit satisfy their corresponding predetermined timing requirements. The predetermined timing requirements can comprise setup time and hold time determined from a digital logic unit design library and/or other suitable timing requirements (e.g., based on the actual application) indicated by chip front-end developers. It is noted that if the predetermined timing requirements cannot be satisfied, the chips may not operate reliably (e.g., execute their logic operations as intended) at a predetermined temperature and voltage. Physical closure can refer to the process for ensuring that all the layout wirings on the chip satisfy a set of predetermined parameters known as Design Rule Checks (DRC). These design rules can be used to check whether all the logic connections are associated with corresponding connections at the physical level and whether the connection constraints are satisfied. It is noted that if the design rule checks are not satisfied, short circuits, open circuit, and other such connection errors can occur in the chips, causing malfunctioning (or unreliable operation) of the chips.
Optimization processes are executed to ensure that the integrated circuit design satisfies the timing requirements for timing closure. The optimization processes include changing the gate area of a digital logic unit to vary the driving capability of the logic unit and/or to vary the delay associated with the logic unit. The optimization processes also include recombining the structure of a buffer or a buffer tree, inserting buffer trees to build and optimize a clock tree, inserting buffer units to satisfy constraint requirements associated with transmission time and load of physical wires, inserting buffer units to satisfy constraint requirements associated with hold time or setup time, inserting one or more additional logic units, etc. Inserting the additional logic units serves to increase the metal layer (generally the lower metal layer associated with the highest wiring density) occupied by the logic units. The new logic connections as a result of the additional logic units consumes additional wiring resources because A) the length of the original metal wires may be increased because of the additional buffer units (e.g., because of a change in the wiring direction), and B) the pin connections of the additional logic units require additional metal vias (i.e., vertical electrical connection between different layers). Thus, the optimization processes to ensure timing closure result in a decrease in the amount of available wiring resources, additional problems because of the added metal wires and metal vias, and an increase in the amount of time to further optimize the wiring resources.
Typically, one or more metal layers and metal vias are changed to ensure that the chip satisfies the DRC for physical closure. However, the changes made to the metal layers and metal vias may directly affect (e.g., increase or decrease) the length of the original metal wires. This can result in a variation in the parameters (e.g., resistance and capacitance) of the metal wires, which in turn can result in a variation in the signal transmission time and in the delay. These changes (e.g., an increase or a decrease in the signal transmission time, the delay, etc.) can affect the timing closure, especially in the regions of the chip where the wiring resources are limited and where it is difficult to change the metal layers and metal vias. In the regions of the chip that are associated with limited wiring resources, a slight change in one part of the region can affect the entire design of the chip. To obtain more wiring resources, some metal connections may have to bypass the regions where the wiring resources are limited. This may increase the length of the original metal wire and may even result in additional metal layers and metal vias. This increase a can further affect the parameters (e.g., resistance and capacitance) of the metal wires which, in turn, can result in a variation in signal transmission time and delay. Thus, the process for ensuring physical closure, especially in the regions where the wiring resources are limited, can result in a variation of the signal transmission time and the delay on the wire which, in turn, can influence the timing closure.